ECE 240 - Digital Logic (Spring 2013)

• Catalog Description
• Syllabus (approximate)
• Academic Assistance Programs
• Lab web page (ECE 241)

Policies

All assignments are collected at the start of class on the specified due date. Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, etc.). Attendance is mandatory. Students who miss five or more class periods will receive a final grade of F for the course. (Arriving late or leaving early is considered absent.)

Text

Digital Design and Computer Architecture, David Harris and Sarah Harris, Morgan Kaufmann, 2007. ISBN10: 0-12-370497-9 (Not the 2nd edition!)

Reading

• Jan 9 - Read chapter 1
• Jan 14 - Read chapter 2
• Feb 8 - Read through section 3.2
• Feb 15 - Read the rest of chapter 3
• Mar 18 - Read section 5.4
• Mar 25 - Read chapter 5 through section 5.2.5 (skip prefix adders)

Homework and Quizzes (20%)

Homework will typically be graded on a 3 point scale: 1-2 points if partially (or poorly) completed; 3 points if completed and apparently correct. All homework will be collected in class at the start of the class. Late homework will not be accepted without prior permission. Students may work together and should check their answers against the posted solutions. There will also be unannounced quizzes throughout the semester, covering the lectures, assigned reading, and homework. Closed book, closed notes.

1. Due Jan 14. Ch. 1: 4, 9, 12
2. Due Jan 18. Ch. 1: 18, 34, 36
3. Due Jan 25. Ch. 1: 43, 44, 49, 50, 60
4. Due Jan 28. Ch. 2: 1(d,e), 2(c,d,e), 4(b,c)
5. Due Jan 30. Ch. 2: 6, 7, 9
6. Due Feb 8. Ch. 2: 28, 30. Implement the following two functions using one 2-4 decoder and additional logic as needed: F1(B,C)=m(0,1,3); F2(A,B,C)=m(0,2,3,5,6,7).
7. Due Feb 15. Ch. 2: 19, 22, 23(b), 24, 32
8. Due Feb 22. Ch. 3:1-4, 6, 7
9. Due Feb 27. Ch. 3: 13; and Mysterious circuits!?!?!?
10. Due Mar 1. Ch. 3: 16, 17, 20 (bring to exam)
11. Due Mar 18. Ch. 3: 24, 26, 28
12. Due Mar 20. Ch. 3: 30, 32. Design an 8-bit “super reg” that can increment, decrement, multiply, or divide - all by 2! (feel free to use muxes)
13. Due Mar 25. Design a system consisting of a FSM and shift register that loads a data in response to GO, locates the right most zero, and asserts a DONE output.
14. Due Mar 29. Ch. 5.40, FSM exercises(Q3 – Q6). Mealy FSM controller for the "Find That Zero" problem.
15. Due Apr 3. Ch 5.14, 15, 16 (no HDL needed)
16. Due Apr 19. Ch. 5.1-3 (Note: for 5.2 the total gate cap is 20 fF and Vdd = 1.2 V.

Exams (80%)

Please bring your own paper, pencils, and erasers to each exam. No calculators.

There will be three semester exams and a comprehensive final, weighted equally. All exams are closed book and closed notes. Make-up exams will not be given without prior permission.

1. Feb 1. Topics List
2. Mar 1. Topics List
3. Apr 5. Topics List
4. Final Exam, May 6 (Mon), 10am - noon. Topics List

Handouts