ECE 241 - Digital Logic Lab (Fall 2013)

Lab TA: Kora Barnes

TA Hours (GJL 210): To Be Determined

Lab will begin the week of August 26 in GJL 210. You will need a computer login to the EEPC network from John Jacksha (JJ). His office is in BEL 207A, but he often sits in BEL 216. His picture is here.

Grades on lab experiments are separate from ECE 240 and determine the grade for ECE 241. There will be approximately fourteen labs throughout the semester and all are mandatory. Failure to complete any lab on time will result in a final course grade of F. Experiments that are not fully functional may be demonstrated and submitted for partial credit until 3 pm on Friday of the week the lab was assigned. To receive full credit for the experiment you must complete and demo it during the lab session. Late assignments are not accepted and students must work alone. Each student should bring the following to each lab.

Lab Experiments

Your pre-lab assignment will be collected at the start of lab. Bring an extra copy for your own use.

  1. Getting to Know your Environment. Report due in lab the week of Sep 2.
  2. Combinational Logic Design. Pre-lab: Preliminary design. Report due in lab the week of Sep 9.
  3. Two-Bit Ripple Carry Adder. Pre-lab: Preliminary design. Report due in lab the week of Sep 16.
  4. Implementing Combinational Logic Circuits. Pre-lab collected at the start of lab. (Be sure to read Section 2.8 from the text!) Report due in lab the week of Sep 23.
  5. Blinky and VHDL! Pre-lab: Read sections 4.0 - 4.2.2 of the text (only VHDL!). Report due in lab the week of Sep 30.
  6. VHDL Adder. Pre-lab: watch the next video and develop a preliminary design. Report due in lab the week of Oct 7.
  7. Structural VHDL and Iterative Circuits. Pre-lab collected at the start of lab (typed or handwritten). Report due in lab the week of Oct 14.
  8. Crazy Counter. Pre-lab collected at the start of lab. Report due in lab the next period.
  9. Son of Crazy Counter! Pre-lab collected at the start of lab. Report due in lab the next period.
  10. Moore or Mealy?!?!? Pre-lab collected at the start of lab. Report due in lab the next period.
  11. Light Dem Lights! Pre-lab collected at the start of lab. Report due in lab the next period.
  12. Wimpy ALU with Muxes! Pre-lab collected at the start of lab (typed or handwritten). Report due in lab the next period
  13. Pico ALU. Pre-lab due at the start of the lab. Report due in lab the next period.
  14. Pico Processor. Pre-lab due at the start of the lab. Report due in ECE 240 on Dec 11.

Basic Process

Download Checklist

Do not download your design to the FPGA (i.e., program the part) until you have completed the following checklist. Failure to do so may damage the component and result in a fine.

Reference Material

Course Specific

Digilent Tutorials

The Dr. J Show: Windows Media Video (*.wmv) files

Xilinx ISE Information

(Most Xilinx docs also loaded in labs under C:\Xilinx\doc)