ECE 241 Digital Logic Lab (Fall 2008)

Lab TA: Damian

Lab Hours: TBD

Grades on lab experiments are separate from ECE 240 and determine the grade for ECE 241. There will be approximately twelve labs throughout the semester and all are mandatory. Failure to complete any lab on time will result in a final course grade of F. (Experiments that are not fully functional may be submitted for partial credit, if on time, but turning in only a report earns little credit.) Late assignments are not accepted. Labs will be conducted in GJL 210. Each student should bring the following to each lab. Students must work alone.

· Lab notebook (for recording information, observations, and data)

· Pre-lab assignment (if applicable), ready to turn in

· Lab handout for scheduled experiment

Lab Experiments

1. Getting to Know your Environment. Report due in lab the week of Sep 1. Must demo by 5 pm, Friday, Aug 29.

Basic Process

· Design your circuit with paper and pencil

· Create new project and enter your design sources (schematics or VHDL)

· Create a test bench waveform and perform behavioral (i.e., pre-synthesis) simulation

· Assign package pins

· Perform synthesis and implementation

· Perform post-route simulation

· Download design and demo

· Print design summary and obtain signature

· Turn in design sources, simulation results, signed design summary, and report

Download Checklist

Do not download your design to the FPGA (i.e., program the part) until you have completed the following checklist. Failure to do so may damage the component and result in a fine.

· Check for any warnings or errors. Some warnings may be ok, but you can not ignore errors. If unsure, check with the instructor

· Verify the part number and package type

· Verify the pin assignment by looking at the pad report

· Verify that the JTAG clock is selected as the “startup clock”

· Verify that the programming cable and power cable are connected

· Verify that the programming switch is in the JTAG position

· No blanks or non-alphanumeric characters in path or file name

· The entity name of a VHDL module must match the file name with a vhd extension

Reference Material

Sample Lab Reports

Digilent Board Documentation (D2XL-DIO1 combo boards)

D2XL->DIO1 Pin Table

Sample UCF file (sample_file.ucf)

Xilinx naming conventions and recommendations

Digilent Videos:

• Creating a schematic
• Performing a simulation
• Design Synthesis (after VHDL intro)
• Circuit Design Download

ISE Tutorials: (Most Xilinx docs loaded in labs under C:\Xilinx\doc)

• Digilent Webpack tutorial
• Getting Started with Xilinx ISE
• Xilinx ISE In Depth Tutorial
• Xilinx ISE Manuals
• Xilinx Library Guide (or see “Functional Categories” under “Libraries Guide” in ISE manual)