Design an up by one, down by two, 3-bit counter as a Moore Finite State Machine. Count direction is determined by a single input, up_dwn_b, and the counter counts up when this signal is a logic one. The counter should "roll over" when it reaches "111", i.e. increment to "000", and decrement past zero when counting down. Implement using a schematic and verify via post-route simulation.
Turn in your details of your design, showing how you developed the Boolean equations for the next state logic. Schematic not necessary for the pre-lab.
Develop a schematic of your counter in the Xilinx ISE and simulate the post-route netlist using Modelsim. Demonstrate the simulation to your instructors and turn in a hardcopy.
Turn in a brief, professional report that describes your design process
and results. Elaborate on any problems you encountered. Finally, attach to your
report hardcopies of your schematic, post-route simulation, and the signed