Use structural VHDL to implement a binary comparator as an iterative circuit. (see section 4.3 of Harris & Harris)
Read section 4.3 of the text and watch the episode of the Dr. J Show, Structural Modeling with VHDL. (You should also watch both videos on Dataflow Modeling if you have not already done so!) Turn in a detailed sketch of your comparator (hand-drawn and photocopied is acceptable), showing how the slices are interconnected, as well as the internal logic of each slice. Also include a draft of your VHDL model.
A binary comparator, like an adder, can be implemented as an iterative
circuit. Implement a 4-bit comparator for comparing two, 4-bit unsigned
numbers, as an iterative circuit with four,
one-bit-slices. An example of a generic iterative circuit is shown below.
Each bit-slice should compare
two single-bit inputs and combine the comparison result with the results of
previous bits to produce three outputs: Greater Than (GT), Less Than (LT), and EQual (EQ). The output logic of an individual slice will
depend upon whether the outputs propagate from lsb to
msb, or vice versa. The boundary output from the last slice
is the final output of the comparator.
Do not use additional
gates to logically combine the individual slice primary outputs!
(The "primary" outputs shown in the figure do not apply to this example.)
Turn in a brief, professional report that describes your design process
and results. Comment on the "efficiency" of VHDL coding styles, e.g., dataflow
versus structural. Elaborate on any problems you encountered. Finally, attach
to your report hardcopies of your VHDL, post-route simulation, and the signed