Moore or Mealy?


Understand the difference between Moore and Mealy Finite State Machines - implementation and timing implications.


Prelab (5 pts) - Due at the start of the lab

Design finite state machine (FSM) bit pattern detectors to detect the bit pattern "010" every time it occurs in a bit string (allow for overlapping sequences). Complete two designs (as separate Xilinx projects!): (1) a Moore machine, and (2) a Mealy machine. Each FSM has data input X and synchronous reset input R, and output Y. Y is asserted when the pattern has been detected. The Moore machine will assert Y in the state after the last symbol was applied. In contrast, the Mealy machine will assert Y while the last bit of the pattern is present.

For both the Moore and Mealy designing, bring to lab:

1.       A state transition diagram/graph

2.       State transition tables

3.       Boolean equations for next‐state logic and output logic

4.       A sketch of the logic circuit. For your state registers use positive‐edge‐triggered flip‐flops with built‐in reset. (Xilinx symbol: FDR)


Experiment (10 pts)

You will enter your designs as schematics and simulate them (behavioral simulation). Design a test bench waveform that includes the following pattern (applied left to right, with the first bit on the left):


Simulate both Moore and Mealy machines with the input applied on the falling edge of the clock. To do this, you will need to follow these instructions.

         Check the "Add Asynchronous Signal Support" box in the "Initial Timing and Clock Wizard" dialog box that opens after creating a testbench waveform. Select "Next".

         Select your clock input as the circuit clock. Select "Next".

         Highlight "Asynchronous Signals" in the upper panel, then add all signals from the lower right panel as asynchronous signals. Select "Next".

You do not need to download your designs to the Digilent boards.


Report (5 pts)

Turn in a brief, professional report that describes your results. Describe, in your own words, the differences and similarities between Mealy and Moore FSM, particularly with respect to the circuit complexity and output timing. Elaborate on any problems you encountered and what you learned. Finally, attach to your report hardcopies of your schematics, all simulations, and the signed project summary.