Investigate the use of VHDL for implementing combinational logic functions.
Turn in a draft of your code (typed or handwritten) at the start of lab. Watch this episode of the Dr. J Show, Dataflow Modeling with VHDL.
Turn in a brief, professional report that describes your design process and results. Comment on the "efficiency" of VHDL compared to schematics. Elaborate on any problems you encountered. Finally, attach to your report hardcopies of your VHDL, post-route simulation, and the signed project summary.