ECE 240  Digital Logic (Fall 2013)
Policies
All assignments are collected at the start of class
on the specified due date. Each assignment should have your name, the course
number, the date, and the assignment designation (e.g., HW1, etc.). Attendance
is mandatory. Students who miss five or more class periods will
receive a final grade of F for the course. (Arriving late or
leaving early is considered absent.)
Text
Digital Design and Computer Architecture, David Harris and Sarah Harris,
Morgan Kaufmann, 2007. ISBN10: 0123704979 (Not the 2nd edition!)
Reading

Aug 26  Read chapter 1

Sep 2  Read chapter 2

Sep 27  Read through section 3.2

Oct 4  Read the rest of chapter 3

Oct 30  Read section 5.4

Nov 6  Read chapter 5 through section 5.2.5 (skip prefix adders)

Nov 20  Read section 5.5

Dec 8  Read section 5.6
Homework and Quizzes (20%)
Homework will typically be graded on a 3 point scale: 12 points if partially
(or poorly) completed; 3 points if completed and apparently correct.
All homework will be collected in class at the start of the
class. Late homework will not be accepted
without prior permission. Students may work together and should check their
answers against the posted solutions. There will also be unannounced quizzes
throughout the semester, covering the lectures, assigned reading, and homework.
Closed book, closed notes.

Due Aug 30. Ch. 1: 4, 9, 12

Due Sep 6. Ch. 1: 18, 34, 36

Due Sep 9. Ch. 1: 43, 44, 49, 50, 60

Due Sep 11. Ch. 2: 1(d,e), 2(c,d,e), 4(b,c)

Due Sep 18. Ch. 2: 6, 7, 9

Due Sep 23. Ch. 2: 28, 30. Implement the
following two functions using a single 24 decoder and
additional logic as needed: F1(B,C)=m(0,1,3); F2(A,B,C)=m(0,2,3,5,6,7).

Due Sep 27. Ch. 2: 19, 22, 23(b), 24, 32

Due Oct 2. Ch. 3:14, 6, 7

Due Oct 9. Ch. 3: 13; and
Mysterious
circuits!?!?!?

Due Oct 16. Ch. 3: 16, 17, 20

Due Oct 23. Ch. 3: 24, 26, 28

Due Nov 6. Ch. 3: 30, 32. Design an 8bit
“super reg” that can increment, decrement, multiply, or divide
 all by 2! (feel free to use muxes)

Due Nov 13. Ch. 5.40;
FSM exercises; Mealy FSM controller for the
"Find That Zero" problem (Friday inclass exercise).

Due Dec 4. Ch. 5.13 (should be 20 fF gate
cap and 1.2 V supply), 14 (no HDL!)

Due Dec 11. Ch. 5.42, 44 (no HDL), 47
Exams (80%)
Please bring your own paper, pencils, and erasers to each exam. No calculators.
There will be four semester exams and a comprehensive final, weighted equally.
All exams are closed book and closed notes. Makeup exams will
not be given without prior permission.

Sep 13. Topic list. (The exam will
be in JEB 104)

Oct 4. Topic list. (The exam
will be in JEB 104)

Oct 25. Topic list. (The exam will
be in JEB 104)

Nov 15. Topic list. (The exam will
be in JEB 104)

Dec 20 (!), 10amNoon, Final Exam. Topic list.
(EXAM will be in BEL 205  our lecture room!!!!)