ECE 240 - Digital Logic (Fall 2008)

Policies

All assignments are collected at the start of class on the specified due date. Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, etc.). Attendance is mandatory. Students who miss five or more class periods will receive a letter grade of F. This course assesses program outcomes (a) and (l) for the CompE and EE programs.

Text

Digital Design and Computer Architecture, David and Sarah Harris, Morgan Kaufmann, 2007. ISBN10: 0-12-370497-9

Reading

  • Aug 25 - Read chapter 1
  • Sep 1- Read chapter 2

Homework (10%)

Homework will typically be graded on a 3 point scale: 1-2 points if partially (or poorly) completed; 3 points if all problems completed (but not necessarily correct). All homework will be collected in class at the start of the class. Late homework will not be accepted without prior permission. Students may work together and should check their answers against the posted solutions.

  1. Due Sep 3. Ch. 1: 4, 9, 12, 18, 34, 36.

Quizzes (20%)

There will be unannounced quizzes throughout the semester, covering the lectures, assigned reading, and homework. Closed book, closed notes.

Exams (70%)

Please bring your own paper, pencils, and erasers to each exam. No calculators.

There will be four semester exams and a comprehensive final, weighted equally. All exams are closed book and closed notes. Make-up exams will not be given without prior permission.

Bonus Points

Periodically there may be impromptu quizzes. Points earned on these quizzes will be added directly to quiz or exam scores. Closed book, closed notes.

Lectures Handouts

Reference Material

Xilinx University Program

Digilent Documentation (D2XL-DIO1 combo boards).

Integrated Circuit Directories