1) Develop a circuit
with two outputs, Z1 and Z2, with the following output behavior. There is one
pair of outputs per clock cycle.
Z1: 0 1 1 0 0 [. . .]
Z2: 1 1 1 1 0 [. . .]
The above sequences
repeat indefinitely. Neatly sketch a gate-level schematic showing flip-flops
and next state logic.
2) Design a Mealy FSM
with two inputs, X and Y, one output, Z, and the following behavior. The FSM
simultaneously monitors both the X and Y inputs looking for the specific
sequences below and asserts Z whenever the last symbol in one or both of the
sequences is applied. Sequences are allowed to overlap, e.g., the last symbol
in a sequence can serve as the first symbol for another sequence, and there is
no timing relationship between the X and Y inputs other than one input bit per
clock cycle. Only the state table/graph is needed.
X: 1 0 1
Y: 1 1 1