ECE 440 – Digital Systems Engineering (Spring 2015)
All assignments are due at the start of class on the specified due date
(by 3 pm PT for outreach studentss). Late assignments will not
be accepted without prior approval. Each assignment should have your
the course number, the date, and the assignment designation (e.g., HW1,
Attendance is mandatory. Students who miss five or more class periods
will automatically receive a final grade of F.
SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, 2ed, Sutherland et al., ISBN: 978-0-387-33399-1. Textbook
The Zynq Book (free PDF download available)
Homework and Quizzes (10%)
Homework will be collected and graded throughout the semester. Students may
work together on homework and should check their answers against the posted
solutions. There may also be unannounced quizzes periodically, perhaps even
daily! It is your responsibility to make sure you are prepared for every
Due Jan 21. HW1
- Due Jan 28. HW2
- Due Feb 4. HW3
- Due Feb 6. What state should be avoided if using a 5-stage LFSR with taps 3 and 5 fedback through an XNOR2? (and why?!?!?)
Feb 18. Referring to Question 1 on the exam, draw out timing waveforms
to support your answers to the following questions: (1) At what rate is
a new output produced? (2) What is the maximum adder delay (in clock
cycles) for this structure? (3) Can the design be improved in any way?
- Due Feb 27. Analyze this amusing little
circuit and explain how the memory
contents are modified as the circuit goes through four complete cycles of
the the four-bit counter.
- Mar 14 (5 pm PT): PDF of detailed project block diagram and an explanation of your algorithm and how the datapath supports it. (Hand-drawn is fine.)
- Due Apr 1. Develop and verify a C function which calculates n! using only addition - no multiplies!
Apr 6. Turn in a detailed block diagram of a datapath and the
associated FSM for implementing the C function. (design it to terminate
in a "DONE" state)
There will be projects throughout the semester, selected to complement the
lectures. Students are to work independently unless specified otherwise, and contact the instructor if
they have questions. Sample reports
Due Jan 23. Complete lab1 of the Vivado Design flow and submit via e-mail the following deliverables as attachments from your UI
account: (1) The Vivado Messages window with all but "status" selected
(PDF); (2) the Vivado Synthesis Report (PDF); your bit file (BIT). You can download the necessary source files here.
- Due Feb 2. Project 2
- Due Feb 9. Project 3
- Due Feb 23. Using the SystemVerilog system tasks for reading and writing to a file, develop a self-checking testbench
for your Project 2 using the following test data: <X,Y> =
<55,89>; <56,35>; <45,72>; <89,55>. (The
full IEEE standard
is available if you are on the UI network!) Use the testbench to perform a post-implementation timing simulation. Deliverables: PDF of
testbench and any files (testvectors and results). No report or project
- Due Mar 4. Create a synthesizable model of the amusing little circuit and perform a behavioral
simulation, monitoring primary I/O and internal signals, then repeat with
post-implementation simulation observing PIO only. (be sure to simulate through four full counter
cycles.) Verify that the memory accesses are the same between the two
simulations. Please turn in PDFs of your SystemVerilog code, the simulations, and a brief
commentatry on your experience and observations.
- Due Mar24 (5 pm PT). Genomatic. E-mail project archive (zip file) and bit file using provided gene_mem.coe and codon_mem.coe. Sadly, no report, but supporting project "documents" gratefully accepted.
Apr 13. Implement the factorial calculator on one of the Zynq boards.
Upon reset the switches are read, with allowable values of 0-5 for
n. Once the calculation is completed, LED0 is asserted and the result
can be viewed by asserting SW0 to blank the DONE LED and then toggling
SW1 to view the LSB (SW1=0) and MSB. Submit a bit file and project
archive. By April 15 submit a single PDF file (see PDFBinder below)
with a brief report describing what you learned from Projects 6 and 7
and any diagrams or simulations that you performed.
Apr 20. Insert an ILA debug core into your factorial design and capture
a screenshot of the state of all registers and your FSM when the outer
loop counter equals 4 and the inner loop counter equals 2 while
calculating 5!. In addition to my helpful(?) lectures, you may find
this video useful, as well as the documentation.
- Due May 4. Carefully follow the steps in Exercise 1C from the The Zynq Book
and verify on a ZYBO or ZedBoard. (Download both the PDF of the
tutorials and the Source ZIP file.) See Dr. J's Lessons Learned
"gotchas!." Submit the following screenshots as deliverables: the block
diagram of your Processing System from Vivado; top portion of the hdf
and mss file/tabs; and the SDK log window (after you have launched the
debugger). Paste them all into a single PDF file. This video walks you through the flow for a different board and design. (slightly different for SDK)
There will be two semester exams and a comprehensive final, weighted equally,
and closed book/open notes. Please bring your own paper,
pencils, and an eraser to each exam.
Feb 11. Topic List
March 25. Topic List
Final Exam, Tues, May 12, 3-5 pm. Topic list
ASIC World - Verilog
Digilent Zedboard and Zybo
www.zeboard.org and Digilent Forum
High Speed Digital Design
PDF Tools: PDFBinder for combining PDF files and doPDF for creating them (or Foxit)