ECE 440 Digital Systems Engineering (Spring 2013)
All assignments are due at the start of class on the specified due date (by
4pm PT two days later for off-campus). Late assignments will not
be accepted without prior approval. Each assignment should have your name,
the course number, the date, and the assignment designation (e.g., HW1, etc.).
Attendance is mandatory. Students who miss five or more class periods
will automatically receive a final grade of F.
Homework and Quizzes (10%)
Homework will be collected and graded throughout the semester. Students may
work together on homework and should check their answers against the posted
solutions. There may also be unannounced quizzes periodically, perhaps even
daily! It is your responsibility to make sure you are prepared for every
Due Jan 14. (a) Fig. 1-1 in the text shows
a detailed design flow for HDL-based ASICS. Briefly compare this to the flow
you followed in the introductory class using Xilinx FPGAs (or similar); (b)
Why might one company choose an FPGA for their product while another develops
a full-custom IC?
Due Jan 23. (a) Figure 2-62 provides the
function table for a "priority decoder". Show how a priority decoder can
be easily constructed from other components presented in section 2.6; (b)
Implement a majority function of three variables using the smallest multiplexer
possible. (i.e., output a 1 when two or more inputs are 1)
Due Jan 28. Exercise 3.7
Due Feb 8. (1) Provide a Verilog model of
fig. P4-1 from the text using Verilog operators and continuous assignment
statements; (2) Repeat the exercise using an always statement; (3) Comment
on the differences between blocking and non-blocking signal assignments within
an always statement; (4) Develop a Verilog model of fig. P4-19, assuming
the resets are synchronous.
Due Feb 27. Exercise 5.49 (a-b), 50. Analyze
this amusing little circuit and explain
how the memory contents are modified as the circuit goes through three complete
cycles of the the four-bit counter.
Due Mar 1. Now, code up the amusing little
circuit and perform a behavioral simulation, monitoring primary I/O and the
RAM contents, then repeat with post-PAR sim observing PIO only. Verify that
the memory accesses are the same between the two simulations. Please turn
in your Verilog code, the simulations, and a brief commentatry on your experience
Due Mar18. Using Jim's ASMD in the solution
for Exercise 5.49, add waveforms for the following signals to this
graph paper: State, Data (show when
valid), P1, P0, R0, and Cntr. A second page of graph paper of the same scale
is included in the PDF.
There will be projects throughout the semester, selected to complement the
lectures. Students are to work independently and contact the instructor if
they have questions. Sample report
Due Jan 30. Project 1
Due Feb 22. Project 2.
Due Mar 20. Project 3.
Due Apr 1. Project 3(a). Perform a behavioral simulation of your Project
3 using a modified version of Jim's testbench, plotting the state of all
state machines, counters and registers, and the first three memory locatons.
(Don't fix your project!) Comment upon what you discover.
Due Apr 22. Project 3(b). Using this
project archive, follow
these steps. This
video will provide helpful screenshots.
(download to your desktop) Don't hesistate to ask for help!
Due Apr 24. Project 4.
There will be two semester exams and a comprehensive final, weighted equally,
and closed book/open notes. Please bring your own paper, a calculator,
pencils, and an eraser to each exam.
Feb 11. Topics
Apr 1. Topics
Final Exam, May 7 (Tues), 3-5pm. Final Topics
ASIC World - Verilog