ECE 440 – Digital Systems Engineering (Spring 2016)

Policies

All assignments are due at the start of class on the specified due date (by 3 pm PT for outreach students). Late assignments will not be accepted without prior approval. Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, etc.). Attendance is mandatory. Students who miss five or more class periods will automatically receive a final grade of F.

Text

Logic Design and Verification Using SystemVerilog, Donald Thomas., ISBN-13: 978-1500385781

Supplemental Text

The Zynq Book (free PDF download available)

Reading

Homework and Quizzes (10%)

Homework will be collected and graded throughout the semester. Students may work together on homework and should check their answers against the posted solutions. There may also be unannounced quizzes periodically, perhaps even daily! It is your responsibility to make sure you are prepared for every class.

  1. Due Jan 20. HW1
  2. Due Jan 27. HW2
  3. Due Feb 3. Exercise 3.1 from SV. (e-mail a single PDF with your code and sims)
  4. Due Feb 5. E-mail a PDF of a neatly drawn block diagram for the "wrapper" portion of Project 3. You may find some of the handouts on the Design Process useful at some point.
  5. Due Feb 10. Analyze this amusing little circuit and explain how the memory contents are modified as the circuit goes through four complete cycles of the the four-bit counter.Send your explaination as a single PDF attachment that includes timing waveforms to illustrate your explaination.

Projects (45%)

There will be projects throughout the semester, selected to complement the lectures. Students are to work independently unless specified otherwise, and contact the instructor if they have questions. Sample reports

  1. Due Jan 25. Complete lab1 of the Vivado Design flow and submit via e-mail the following deliverables as attachments from your UI account: (1) The Vivado Messages window with all but "status" selected (PDF); (2) the Vivado Synthesis Report (PDF); your bit file (BIT). You can download the necessary source files here. Indicate in your e-mail which board you used: Zybo or Zedboard.
  2. Due Feb 1. Project 2
  3. Due Feb 8. Project 3

Exams (45%)

There will be two semester exams and a comprehensive final, weighted equally, and closed book/open notes.  Please bring your own paper, pencils, and an eraser to each exam.

  1. Feb 17. Topic List
  2. March 30. Topic List
  3. Final Exam,  Wed, May 11, 3-5 pm. Topic list

Lecture Information

Lecture Overheads

Class Handouts

Reference Material

Sutherland HDL
Sunburst Design
ASIC World - Verilog

Digilent Zedboard and Zybo
www.zeboard.org
and Digilent Forum
Xilinx Documentation
High Speed Digital Design

Drawing tool
Timing Diagram Tool
LaTeX2e, the User Guide, and a Not so Short Introduction
proTeXt for Wndows (includes TeXStudio and MiKTeX
PDF Tools: PDFBinder for combining PDF files and doPDF for creating them (or Foxit)