ECE 440 – Digital Systems Engineering (Spring 2017)

Policies

All assignments are due at the start of class on the specified due date (by 3 pm PT for outreach students). Late assignments will not be accepted without prior approval. Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, etc.). Attendance is mandatory. Students who miss five or more class periods will automatically receive a final grade of F.

Text

Logic Design and Verification Using SystemVerilog, Donald Thomas., ISBN-13: 978-1500385781

Supplemental Text

The Zynq Book and the Tutorials (free PDF download available)

Reading

Homework and Quizzes (10%)

Homework will be collected and graded throughout the semester. Students may work together on homework and should check their answers against the posted solutions. There may also be unannounced quizzes periodically, perhaps even daily! It is your responsibility to make sure you are prepared for every class.

  1. Due Jan 18. HW1
  2. Due Jan 25. HW2
  3. Due Feb 1. Exercise 3.1 from SV. (e-mail a single PDF with your code and sims)
  4. Due Feb 3. E-mail a PDF of a neatly drawn block diagram for the "wrapper" portion of Project 3. You may find some of the handouts on the Design Process useful at some point.
  5. Due Feb 13. Analyze this amusing little circuit and explain how the memory contents are modified as the circuit goes through four complete cycles of the the four-bit counter.Send your explaination as a single PDF attachment that includes timing waveforms to illustrate your explaination.
  6. Due Feb 27. E-mail a PDF of a nealty drawn block diagram of your approach for Project 5, along with a written summary of your approach. Be sure to identify any necessary state machines and completely label all status and control signals with recognizable names.

Projects (60%)

There will be projects throughout the semester, selected to complement the lectures. Students are to work independently unless specified otherwise, and contact the instructor if they have questions. Sample reports

  1. Due Jan 20. Complete lab1 of the Vivado Design flow on the Zybo board and submit via e-mail the following deliverables as attachments from your UI account: (1) The Vivado Messages window with all but "status" selected (PDF); (2) the Vivado Synthesis Report (PDF); your bit file (BIT). You can download the necessary source files here.
  2. Due Jan 30. Project 2
  3. Due Feb 6. Project 3
  4. Due Feb 22. Create a synthesizable model of the amusing little circuit and perform a behavioral simulation, monitoring primary I/O and internal signals, then repeat with post-implementation simulation observing PIO only. (be sure to simulate through four full counter cycles.) Verify that the memory accesses are the same between the two simulations. Please e-mail a single PDF of your SystemVerilog code, the simulations, and a brief commentatry on your experience and observations.
  5. Due Mar 3 (10 pm). Project 5
  6. Due Mar 12 (5 pm). Add an ILA to the amusing memory circuit from Project 4 and use it to capture all of the memory I/O (except for the clock!). Deliverables: E-mail a single PDF with a screen capture of the triggered waveforms using the same trigger spec as Dr. J and a brief paragraph on any trials and tribulations.
  7. Mar 27 (10 pm). GenomaticSubmit project archive by due data and a brief report by class on Mar 31.
  8. Apr 3 (10 pm). Carefully follow the steps in Exercise 1C from the The Zynq Book and verify on a ZYBO. (Download both the PDF of the tutorials and the Source ZIP file.) See Dr. J's Lessons Learned for "gotchas!" Submit the following screenshots as deliverables: the block diagram of your Processing System from Vivado; top portion of the hdf and mss file/tabs; and the SDK log window (after you have launched the debugger). Paste them all into a single PDF file like this. E-mail the file as an attachment. (Mine was for the Zedboard.)
  9. Apr 10 (10 pm). Complete Exercise 4A out of the Zynq Tutorial Book (2ed) on the Zybo, but using Verilog. Zip-n-Ship your project as an e-mail attachment, along with a PDF of the completed Block Diagram and the terminal window (Figure 4.21). 
  10. Apr 20 (10 pm). Factorial Co-processor
  11. May 1 (10 pm). CPU - AXI FIFO - GCD - SPI!

Exams (30%)

There will be two semester exams and a comprehensive final, weighted equally, and closed book/computer, open notes (handwritten).  Please bring your own paper, pencils, and an eraser to each exam.

  1. Feb 15. Topics list
  2. Mar 29. Topics list
  3. Final exam. Wed, May 10, 12:30-2:30 pm. Topics list

Lecture Information

Lecture Overheads

Class Handouts

Reference Material

Sutherland HDL
Sunburst Design
ASIC World - SystemVerilog

EDA Playground
Digilent Zybo board and Resource Center
Xilinx Documentation and Workshops
Silca EMEA projects on GitHub
High Speed Digital Design
Drawing tools (CFD, DFD, block diagrams): Lucidchart and draw.io
Timing Analyzer or Wavedrom tools for drawing timing diagram
LaTeX2e, the User Guide, and a Not so Short Introduction
proTeXt for Wndows (includes TeXStudio and MiKTeX
PDF Tools: PDF Creator (create and combine), PDFBinder for combining PDF files and doPDF for creating them (or Foxit)