ECE 440 – Digital Systems Engineering (Spring 2015)


All assignments are due at the start of class on the specified due date (by 3 pm PT for outreach studentss). Late assignments will not be accepted without prior approval. Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, etc.). Attendance is mandatory. Students who miss five or more class periods will automatically receive a final grade of F.


SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, 2ed, Sutherland et al., ISBN: 978-0-387-33399-1. Textbook web page

Supplemental Text

The Zynq Book (free PDF download available)


Homework and Quizzes (10%)

Homework will be collected and graded throughout the semester. Students may work together on homework and should check their answers against the posted solutions. There may also be unannounced quizzes periodically, perhaps even daily! It is your responsibility to make sure you are prepared for every class.

  1. Due Jan 21. HW1
  2. Due Jan 28. HW2
  3. Due Feb 4. HW3

Projects (45%)

There will be projects throughout the semester, selected to complement the lectures. Students are to work independently unless specified otherwise, and contact the instructor if they have questions. Sample report

  1. Due Jan 23. Complete lab1 of the Vivado Design flow and submit via e-mail the following deliverables as attachments from your UI account: (1) The Vivado Messages window with all but "status" selected (PDF); (2) the Vivado Synthesis Report (PDF); your bit file (BIT). You can download the necessary source files here.
  2. Due Feb 2. Project 2
  3. Due Feb 9. Project 3

Exams (45%)

There will be two semester exams and a comprehensive final, weighted equally, and closed book/open notes.  Please bring your own paper, pencils, and an eraser to each exam.

  1. Feb 11.
  2. March 25.
  3. Final Exam,  Tues, May 12, 3-5 pm.

Lecture Information

Lecture Overheads

Class Handouts

Reference Material

Sutherland HDL

Sunburst Design

ASIC World - Verilog

Digilent Zedboard and Zybo and Digilent Forum

Xilinx Documentation

High Speed Digital Design