All assignments are due at the start of class on the specified due date (by 3 pm PT for outreach studentss). Late assignments will not be accepted without prior approval. Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, etc.). Attendance is mandatory. Students who miss five or more class periods will automatically receive a final grade of F.
SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, 2ed, Sutherland et al., ISBN: 978-0-387-33399-1. Textbook web page
The Zynq Book (free PDF download available)
Homework will be collected and graded throughout the semester. Students may work together on homework and should check their answers against the posted solutions. There may also be unannounced quizzes periodically, perhaps even daily! It is your responsibility to make sure you are prepared for every class.
There will be projects throughout the semester, selected to complement the lectures. Students are to work independently unless specified otherwise, and contact the instructor if they have questions. Sample report
There will be two semester exams and a comprehensive final, weighted equally, and closed book/open notes. Please bring your own paper, pencils, and an eraser to each exam.
ASIC World - Verilog
Digilent Zedboard and Zybo
www.zeboard.org and Digilent Forum
High Speed Digital Design