ECE 440 – Digital Systems Engineering (Spring 2018)
All assignments are due at the start of class on the specified due date
(by 3 pm PT for outreach students). Late assignments will not
be accepted without prior approval. Each assignment should have your
the course number, the date, and the assignment designation (e.g., HW1,
Attendance is mandatory. Students who miss five or more class periods
will automatically receive a final grade of F.
Logic Design and Verification Using SystemVerilog (reviesed), Donald Thomas., ISBN-13: 978-1523364022. March 2016
The Zynq Book and the Tutorials (free PDF download available)
Jan 10 - chapters 1 and 2 of the SystemVerilog text (SV) and chapters 1 and 2 of the Zynq Book (ZB)
- Jan 17 - chapters 3 and 4 (SV)
- Jan 24 - chapter 3 (ZB)
- Jan 29 - Xilinx application note on LFSR
- Jan 31 - Distributed Memory slides and Xilinx Distributed Memory Generator
- Feb 12 - Block Memory slides and Xilinx Block Memory Generator
- Feb 16 - chapter 5 (SV)
Homework and Quizzes (10%)
Homework will be collected and graded throughout the semester. Students may
work together on homework and should check their answers against the posted
solutions. There may also be unannounced quizzes periodically, perhaps even
daily! It is your responsibility to make sure you are prepared for every
Due Jan 17. HW1
- Due Jan 22. HW2
- Due Jan 29. Exercise 3.1 from SV. (e-mail a single PDF with your code and sims)
- Due Feb 2. E-mail a PDF of a neatly drawn block diagram for the "wrapper" portion of Project 3. You may find some of the handouts on the Design Process useful at some point.
- Due Feb 12. Analyze this amusing little
circuit and explain how the memory
contents are modified as the circuit goes through four
complete cycles of the the four-bit counter.Send your explaination as a
single PDF attachment that includes timing waveforms to illustrate your
- Due Feb 26. E-mail a PDF of a nealty drawn block diagram of your approach
for Project 5, along with a written summary of your approach. Be sure
to identify any necessary state machines and completely label all
status and control signals with recognizable names.
There will be projects throughout the semester, selected to complement the
lectures. Students must work independently and contact the instructor if
they have questions. No collaboration is permitted. Sample reports
Due Jan 19. Complete lab1 of the Vivado Design flow on the Zybo board and submit via e-mail the following deliverables as attachments from your UI
account: (1) The Vivado Messages window with all but "status" selected
(PDF); (2) the Vivado Synthesis Report (PDF); your bit file (BIT). You can download the necessary source files here.
- Due Jan 26. Project 2
- Due Feb 5. Project 3
- Due Feb 20 (by 10 pm). Create a synthesizable model of the amusing little circuit and perform a behavioral
simulation, monitoring primary I/O and internal signals, then repeat with
post-implementation simulation observing PIO only. (be sure to simulate through four full counter
cycles.) Verify that the memory accesses are the same between the two
simulations. Please e-mail a single PDF of your SystemVerilog code, the simulations, and a brief
commentatry on your experience and observations.
- Due Mar 2 (e-mail archive by 10 pm; PDF report 48 hours later). Project 5
There will be two semester exams and a comprehensive final, weighted equally,
and closed book/computer, open notes (handwritten only). Please bring your own paper,
pencils, and an eraser to each exam.
- Feb 14. Topics
- Mar 28.
- May 10, Thurs, 12:30-2:30 pm.
ASIC World - SystemVerilog
Digilent Zybo board and Resource Center
Documentation and Workshops
Silca EMEA projects on GitHub
High Speed Digital Design
Drawing tools (CFD, DFD, block diagrams): Lucidchart and draw.io
Timing Analyzer or Wavedrom tools for drawing timing diagram
LaTeX2e, the User Guide, and a Not so Short Introduction
proTeXt for Wndows (includes TeXStudio and MiKTeX
PDF Tools: PDF Creator (create and combine), PDFBinder for combining PDF files and doPDF for creating them (or Foxit)