ECE 440 – Digital Systems Engineering (Spring 2014)
All assignments are due at the start of class on the specified due date (by
4pm PT, two calendar days later for off-campus). Late assignments will not
be accepted without prior approval. Each assignment should have your name,
the course number, the date, and the assignment designation (e.g., HW1, etc.).
Attendance is mandatory. Students who miss five or more class periods
will automatically receive a final grade of F.
Homework and Quizzes (10%)
Homework will be collected and graded throughout the semester. Students may
work together on homework and should check their answers against the posted
solutions. There may also be unannounced quizzes periodically, perhaps even
daily! It is your responsibility to make sure you are prepared for every
Due Jan 22. (a) Fig. 1-1 in the text shows
a detailed design flow for HDL-based ASICS. Briefly compare this to the flow
you followed in the introductory class using Xilinx FPGAs (or similar); (b)
Why might one company choose an FPGA for their product while another develops
a full-custom IC?
Due Jan 24. (a) Figure 2-62 provides the
function table for a "priority decoder". Show how a priority decoder can
be easily constructed from other components presented in section 2.6; (b)
Implement a majority function of three variables using the smallest multiplexer
possible. (i.e., output a 1 when two or more inputs are 1)
Due Jan 29. Exercise 3.7.
Digital Review problems.
Due Jan 31.
Digital Design Problems.
Due Mar 3. Analyze this amusing little
circuit and explain how the memory
contents are modified as the circuit goes through four complete cycles of
the the four-bit counter.
Due Mar 14. Why are Gray code pointers used to implement FIFOs that buffer
two separate clock domains?
- Due Mar 28. Detailed block diagram of project 4. (as a planning tool)
There will be projects throughout the semester, selected to complement the
lectures. Students are to work independently and contact the instructor if
they have questions. Sample report
Due Feb 3. Project 1
Due Feb 21. Project 2.
Due March 10. Now, code up the amusing little circuit and perform a behavioral
simulation, monitoring primary I/O and the RAM contents, then repeat with
post-PAR sim observing PIO only. (be sure to simulate through four full counter
cycles.) Verify that the memory accesses are the same between the two
simulations. Please turn in your Verilog code, the simulations, and a brief
commentatry on your experience and observations.
- Due Apr 7. Project 4. Solution slides.
- Due Apr 25. Project 5.
- Due May 7. ChipScope
There will be two semester exams and a comprehensive final, weighted equally,
and closed book/open notes. Please bring your own paper, a calculator,
pencils, and an eraser to each exam.
Feb 12. Topics
March 26. Topics
Final Exam, Thurs, May 15, 3-5pm.
ASIC World - Verilog