ECE 440 – Digital Systems Engineering (Spring 2020)
As a result of the worldwide pandemic, the following modifications will be made.
All assignments are due electronically by the start of class on the specified due date, unless otherwise noted. Late assignments will not
be accepted without prior approval. Each assignment should have your
the course number, the date, and the assignment designation (e.g., HW1,
Attendance is mandatory. Students who miss five or more class periods
will automatically receive a final grade of F.
- A final grade of 70% will be required to earn a grade of "Pass" if you take the course pass/fail. (not recommended!)
- Letter grades will still follow the normal A-90%, B-80%, etc.
- Exam 2 and the Final will be distributed via BbLearn and returned by sharing a OneDrive folder with all materials
- Written material, such as homework and project reports should be
e-mailed as PDF attachments with appropriate filenames and subject
- Xilinx project files should be archived using Vivado 2016.4 and then shared via OneDrive.
- Refresh your web browser and read your VandalMail frequently.
- Ask more questions than usual, particularly if you need assistance!
Logic Design and Verification Using SystemVerilog (reviesed), Donald Thomas., ISBN-13: 978-1523364022. March 2016
The Zynq Book and the Tutorials (free PDF download available)
Jan 15 - chapters 1 and 2 of the SystemVerilog text (SV) and chapters 1 and 2 of the Zynq Book (ZB)
- Jan 22 - chapters 3 and 4 (SV)
- Jan 29 - chapter 3 (ZB)
- Feb 3 - Xilinx application note on LFSR
- Feb 5 - Distributed Memory slides and Xilinx Distributed Memory Generator
- Feb 10 - Block Memory slides and Xilinx Block Memory Generator
- Feb 12 - Chapter 5 (SV)
- Feb 21 - Watch this video on inserting Vivado Debug cores and chapter 6 (SV)
- Feb 29 - Download the tutorials book and source from the Zynq Book site. Read through Section 1, "First Designs on Zynq", and watch this video.
- Mar 4 - Read this paper on
- Mar 9 - Synchronous FIFO intro
- Mar 13 - Cliff Cummings' paper on asynchronous FIFO design
- Mar 25 - Designing a Custom AXI-lite Slave Peripheral
- Apr 10 - Ch 7 (SV)
Homework and Quizzes (10%)
Homework will be collected and graded throughout the semester. Students may
work together on homework and should check their answers against the posted
solutions. There may also be unannounced quizzes periodically, perhaps even
daily! It is your responsibility to make sure you are prepared for every
Due Jan 22. HW1
- Due Jan 29. HW2
- Due Feb 3. Exercise 3.1 from SV. Note: rstN is asynchronous and active
low. Be sure to verify control signal priority. (e-mail a single PDF
with your code and sims)
- Due Feb 5. E-mail a PDF of a neatly drawn block diagram for the "wrapper" portion of Project 3. You may find some of the handouts on the Design Process useful at some point.
- Due Feb 12. Analyze this amusing little
circuit and explain how the memory
contents are modified as the circuit goes through four
complete cycles of the the four-bit counter.Send your explaination as a
single PDF attachment that includes timing waveforms to illustrate your
- Due Feb 19. Exercise 5.2 from SV, but only the design - no SystemVerilog model or testbench.
- Due Feb 24. E-mail a PDF of a neatly drawn block diagram of your approach
for Project 5, along with a written summary of your approach. Be sure
to identify any necessary state machines and completely label all
status and control signals with recognizable names.
There will be projects throughout the semester, selected to complement the
lectures. Projects must be submitted using the same software version as used in the lab, BEL 215. Students must work independently and contact the instructor if
they have questions. No collaboration is permitted. Sample reports
Due Jan 24. Complete lab1 of the Vivado Design flow on the Zybo board and submit via e-mail the following deliverables as attachments to a single e-mail from your UI
account: (1) The Vivado Messages window with all but "status" selected, and the Vivado Synthesis Report as a single PDF file; and (2) your bit file (BIT). You can download the necessary source files here.
- Due Jan 31. Project 2
- Due Feb 10. Project 3
- Due Feb 17. Create a synthesizable model of the amusing little
circuit using distributed memory and perform a behavioral simulation,
monitoring primary I/O and internal signals, then repeat with
post-implementation simulation observing PIO only. (be sure to simulate through four full counter
cycles.) Verify that the memory accesses are the same between the two
simulations. Please e-mail a single PDF of your SystemVerilog code, the simulations, and a brief
commentary on your experience and observations.
- Due Feb 28. BMEM-GCD-SPI
- Due Mar 8 (by 10 pm). Add an ILA to the amusing memory circuit from Project 4 and use
it to capture all of the memory I/O (except for the clock!).
Deliverables: Submit a single PDF with a screen capture of the
triggered waveforms using the same trigger spec
as Dr. J and a brief
paragraph on any trials and tribulations. Note: You will want to create
an XDC file that assignes the primary inputs and outputs to package
pins. Note: Please submit by placing the PDF on your UI OneDrive and then sharing the file with me. (You will need to be on the UI network or connected via a VPN.)
- Due by Mar 15 (10 pm). Carefully follow the steps in Exercise 1A-C from the The Zynq Book
and verify on a ZYBO. (Download both the PDF of the
tutorials and the Source ZIP file.) See Dr. J's Lessons Learned
"gotchas!" Submit the following screenshots as deliverables: the block
diagram of your Processing System from Vivado; top portion of the hdf
and mss file/tabs; and the SDK log window (after you have launched the
debugger). Paste them all into a single PDF file like this. E-mail the file as an attachment. (Mine was for the Zedboard, so yours will look different.)
- Due by Mar 29 (10 pm). Genomatic. Share via OneDrive the project archive by the due date and e-mail a brief report (PDF) by 10 pm on March 31.
- Due by Apr 6 (10 pm). Complete Exercise 4A up through Step (bb) out of the Zynq
Tutorial Book (2ed) on the Zybo, but using Verilog. Zip-n-Share your
project via OneDrive. E-mail a brief report of your trials and tribulations as an e-mail attachment (PDF) by 10 pm on Apr 8.
- Due by Apr 17 (10 pm). Factorial Co-processor UPDATE!!! Post-synthesis simulation of the factorial module with a pulse synchronizer only. No block diagram, AXI registers, or SDK.
- Due by May 3 (10 pm). AXI Traffic Generator to AXI Stream FIFO to
Factorial Co-processor to Primary Outputs. (Post-Synth timing sim only and no
There will be two semester exams and a comprehensive final, weighted equally,
and closed book/computer, open notes (handwritten only). Please bring your own paper,
pencils, and an eraser to each exam.
- Feb 21. Topics
- Apr 3. Topics. (Available for download on BbLearn at 1:30 pm PDT. Return by sharing a OneDrive folder with text and images.)
- May 11, 12:45-2:45 pm PDT. (Download from BbLearn and share via OneDrive folder.) Topics.
ASIC World - SystemVerilog
Digilent Zybo board and Resource Center
Digilent Analog Discovery 2 Resource Page
Documentation and Workshops
Silca EMEA projects on GitHub
High Speed Digital Design
Drawing tools (CFD, DFD, block diagrams): Lucidchart and draw.io
Timing Analyzer or Wavedrom tools for drawing timing diagram
LaTeX2e, the User Guide, and a Not so Short Introduction
proTeXt for Wndows (includes TeXStudio and MiKTeX
PDF Tools: PDF Creator (create and combine), PDFBinder for combining PDF files and doPDF for creating them (or Foxit)