ECE 440 – Digital Systems Engineering (Spring 2017)

Policies

All assignments are due at the start of class on the specified due date (by 3 pm PT for outreach students). Late assignments will not be accepted without prior approval. Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, etc.). Attendance is mandatory. Students who miss five or more class periods will automatically receive a final grade of F.

Text

Logic Design and Verification Using SystemVerilog, Donald Thomas., ISBN-13: 978-1500385781

Supplemental Text

The Zynq Book and the Tutorials (free PDF download available)

Reading

Homework and Quizzes (10%)

Homework will be collected and graded throughout the semester. Students may work together on homework and should check their answers against the posted solutions. There may also be unannounced quizzes periodically, perhaps even daily! It is your responsibility to make sure you are prepared for every class.

  1. Due Jan 18. HW1
  2. Due Jan 25. HW2
  3. Due Feb 1. Exercise 3.1 from SV. (e-mail a single PDF with your code and sims)

Projects (60%)

There will be projects throughout the semester, selected to complement the lectures. Students are to work independently unless specified otherwise, and contact the instructor if they have questions. Sample reports

  1. Due Jan 20. Complete lab1 of the Vivado Design flow on the Zybo board and submit via e-mail the following deliverables as attachments from your UI account: (1) The Vivado Messages window with all but "status" selected (PDF); (2) the Vivado Synthesis Report (PDF); your bit file (BIT). You can download the necessary source files here.
  2. Due Jan 30. Project 2

Exams (30%)

There will be two semester exams and a comprehensive final, weighted equally, and closed book/computer, open notes (handwritten).  Please bring your own paper, pencils, and an eraser to each exam.

  1. Feb 15
  2. Mar 29
  3. Final exam. Wed, May 10, 12:30-2:30 pm

Lecture Information

Lecture Overheads

Class Handouts

Reference Material

Sutherland HDL
Sunburst Design
ASIC World - Verilog

EDA Playground
Digilent Zybo board and Resource Center
www.zeboard.org and Digilent Forum
Xilinx Documentation
High Speed Digital Design

Drawing tools (CFD, DFD, block diagrams): Lucidchart and draw.io
Timing Analyzer or Wavedrom tools for drawing timing diagram
LaTeX2e, the User Guide, and a Not so Short Introduction
proTeXt for Wndows (includes TeXStudio and MiKTeX
PDF Tools: PDF Creator (create and combine), PDFBinder for combining PDF files and doPDF for creating them (or Foxit)