ECE 440 – Digital Systems Engineering (SPR 2008 – 3X/week)

Catalog Description
Textbook web page
Textbook Companion Site
Syllabus (approximate)
Academic Assistance Programs
Post a comment or question to the class e-mail list, ece440_at_mrc.uidaho.edu

Policies

All assignments are due at the start of class on the specified due date. Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, etc.). Attendance is mandatory. Students who miss five or more class periods will automatically receive a final grade of F. This course assesses program outcomes (h), (j), and (l).

Reading

Jan 9 - Read digital logic review and chapter 1
Jan 14 - Read chapter 2, skim chapter 3
Jan 16 - Read chapters 4 and 5
Feb 6 - Read chapter 6
Feb 11 - Read this chapter on Datapath and Control. Pay particular attention to the material on “Circuit Timing” near the end.
Feb 15 - Read chapter 7
Feb 18 - Read chapter 8
Feb 25 - Read chapter 10
Mar 6 - Read chapter 9
Mar 31 – Read 16.5-8 and this paper on synchronization errors
Apr 4 – Read “Practical design for transferring signals between clock domains” and “Crossing the abyss: asynchronous signals in a synchronous world”
Apr 10 – Read 16.9 and this paper on asynchronous FIFO design
Apr 25 – Read this paper on Delay-Locked Loops

Homework and Quizzes (15%)

Homework will be collected and graded throughout the semester. Students may work together on homework and should check their answers against the posted solutions. There will also be unannounced quizzes periodically, perhaps even daily! It is your responsibility to make sure you are prepared for every class.

1. Due Jan 16. 1.2, 5, 6. (1) Why are there different “views” of the same design and how is each used? Pick some object and describe the three main views. (2) How is simulation used throughout the design process? (3) What might cause a designer or manufacturer to select one technology over another? Describe an example. (4) Perform a back-annotated simulation of an inverter in a Xilinx FPGA and determine the pin-to-pin delay for rising and falling outputs.

2. Due Jan 23. 2.2, 7, 11

3. Due Jan 30. 3.2, 5, 8 (a,b); 4.1, 2, 6; 5.1-3, 5, 8

4. Due Feb 13. 6.1, 3, 6, 13

5. Due Feb 15. 6.12. Synthesize the VHDL code for Question 5 on Exam 1. Does Xilinx implement separate adders, or a single adder/subtractor? Support your conclusion.

6. Due Feb 22. 7.1, 2, 4 (skip ASIC synthesis)

7. Due Feb 27. 7.7 (except ASIC synth)

8. Due Mar 5. 8.7, 10 (block diagram only, no code), 11, 12.

9. Due Mar 19. 10.2, 4, 10, 12 (state diagram only for all problems!)

10. Due Mar 24. Detailed block diagram of I2C Master project, including datapath and FSM I/O. State graphs not necessary.

11. Due Apr 18. 16.4, 5 (a), 6 (a)

12. Due Apr 23. 16.9, 10, 13 (block diagram and state diagrams only, no code)