Using the FPGA and DAC on the Spartan 3E Starter Board, generate a periodic waveform on pin A of header J5 by repeatedly reading samples out of an embedded ROM. The ROM contents will be provided via a coefficient f (COE) file, containing one period of the waveform. Upon reset, the design will repeatedly read from the ROM and send the appropriate data to the DAC over the SPI bus, and ensuring that the samples are equally spaced in time.
A full period of the waveform will be represented using 64 samples, eight bits each, utilizing a 64 Byte ROM. Since the DAC is a 12-bit DAC, each sample read from the ROM should be multiplied by sixteen. The DAC output should update approximately every microsecond.
· Completed Xilinx Design Summary (after generating the configuration file)
· Hand-drawn block diagram of your design at the RTL level
· Hardcopy of your VHDL code
· E-mail a mime-encoded bit file as an attachment to Dr. J from your UI e-mail address. The subject should be "ECE 440 Project 3 bit file".
· A brief (e.g., ~two pages), professional report. In your report, provide a technical overview of your design, how you addressed any technical aspects, problems you encountered and what you learned from the project.