Implement the Super Register from Project 1 on the Spartan 3E Starter Board from Digilent.
· "BTN South" will reset the design and "BTN West" will serve as the enable.
· The function inputs, f(1:0), will come from the rotary switch. ("rot_a" assigned to "f(1)").
· The buttons and rotary switch inputs will be debounced.
· The register data inputs, d(3:0), will come from switches SW3-SW0.
· The register data inputs, f(1:0), will also drive two of the LEDs (to simplify testing!) J
· The register outputs, q(3:0), will drive LEDs LD3-LD0.
· The 50 MHz board clock will be divided down using an LFSR to produce a frequency of approximately 2 Hz for the Super Register.
· A block diagram of your design at the "register-level", showing major components and interconnect signals (similar to the GCD diagram). Here is another sample. (neatly drawn by hand is fine)
· Completed Xilinx Design Summary (after generating configuration file)
· VHDL code
· Perform a PAR simulation of your design, but with a clock divider that reduces a 50 MHz clock frequency to approximately (50/4) MHz.
· E-mail a mime-encoded bit file as an attachment to Dr. J from your UI e-mail address. The subject should be "ECE 440 Project 2 bit file".
· A brief (e.g., two pages), professional report. In your report, provide a technical overview of your design and, in particular, how you addressed the technical aspects of dividing down the clock and interfacing to the input devices (e.g., switch, etc.). Also discuss any problems you encountered and what you learned from the project.
You will need to refer to the User Guide for the Starter Board, available from the Digilent web site, for pin assignments, etc. In particular, pay close attention to the configuration requirements for the button and switch inputs.
Refer to the Xilinx application note, XAPP052, for information on implementing an LFSR.