ECE 445 - Intro to VLSI Design (Fall 2014)

Policies

All assignments are due at the start of class on the specified due date. (Outreach students: Your assignments are due by 3 pm PT.) Each assignment should have your name, the course number, the date, and the assignment designation (e.g., HW1, P2, etc.).  No extensions without prior arrangements. Attendance is mandatory. Students who miss five or more class periods will receive a letter grade of F.

Text

CMOS VLSI Design, 4th ed., Weste and Harris, Addison-Wesley, 2011. ISBN10: 0-321-54774-8

Reading

Homework and Quizzes (20%)

Homework problems will typically be graded on a 3 point scale: 1-2 points if partially (or poorly) completed; 3 points if the problem is completed and appears correct. All homework will be collected in class at the start of the class. Late homework will not be accepted without prior permission. Students may work together and should check their answers against the posted solutions. There may also be unannounced quizzes periodically, perhaps even daily! It is your responsibility to make sure you are prepared for every class.

  1. Aug 29. Ex. 1.6, 9(b), 13-15.
  2. Sep 5.  Ex. 2.1, 3-5, 7-8.
  3. Sep 10. Ex. 3.1, 4, 6, 7.

Projects (20%)

There will be three semester projects of increasing difficulty and weight.
  1. Oct 8.
  2. Nov 5.
  3. Dec 5.

Exams (60%)

Please bring your own paper, a calculator, and pencil to each exam.

There will be three semester exams and a final, equally weighted and closed book/closed notes. (Formulas will be provided.)

  1. Sep 17.
  2. Oct 15.
  3. Nov 12.
  4. Dec 19, Fri, 10 am - noon.

Lecture Material

Reference Material

Textbook web page

VLSI Information